1. They are not used for RTL but rather verification, correct? They would not be synthesizable.

  2. Do they have better memory management features in turn optimizing program time? If I recall correctly, System Verilog has an automatic garbage collector, so there is no need to deallocate memory.

  3. The official IEEE documentation does a great job of explaining how they work. I am just wondering in what scenarios I would use one vs an array. One guess would be that they have associated methods that allow for easier data manipulation?

Thank you in advance for your knowledge and expertise.

1 Answer

  1. A queue can be synthesisable if it has a bounded maximum size. Only a few synthesis tools support it, probably none of the FPGA synthesis tools.
  2. The key advantage with a queue is in efficiency adding/removing one element from the array, especially when accessed at the head or tail of the queue. A dynamic array may require reallocation and copying the entire array when modifying its size. The penalty for a queue is the extra time it takes to access elements in the middle of the queue, and extra space compared with the same number of element of a dynamic array.
  3. I hope that 2 answers this question.

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