I have in VHDL a code segment which makes me unsure if it's right: a and b are std_logic_vectors. c1 and c0 are std_logic. Is this correct written? Especially the part "c1 = '1' and c0 = '0'" struggels with me.
if unsigned(a) > unsigned(b) then assert(c1 = '1' and c0 = '0') Edit: Here is a bigger code segment:
signal a: std_logic_vector(3 downto 0); signal b: std_logic_vector(3 downto 0); signal c1: std_logic; signal c0: std_logic; begin TEST: forBitComperator port map(a, b, c1, c0); process begin for i in 0 to 2**4-1 loop for k in 0 to 2**4-1 loop wait for 0 ns; a <= conv_std_logic_vector(i, 4); b <= conv_std_logic_vector(k, 4); if i > k then assert c1 = '1' and c0 = '0' report "error "; end if; end loop; end loop; wait; end process; end; 1 Answer
The parts you were unsure about are correct. c0, c1, '0' and '1' are all std_logic, so it is correct to compare them in this way. (In VHDL = is the equality comparison operator. It doesn't perform an assignment, like in many software programming languages). The result of each comparison is a boolean (true or false) so can be used with an assert statement.
The only part that I think is really wrong is that you must end your if with an end if. It is usually also recommended that whenever you use assert, you report an error message and set a severity (e.g. note, warning, error or failure, depending on how serious the error is). Of course, it must also be terminated with ;.
Therefore:
if unsigned(a) > unsigned(b) then assert c1 = '1' and c0 = '0' report "<Error message>" severity warning; end if; 
