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I'd like to understand the syntax used in the line of code below where an alternate name is created using an ALIAS declaration. Specifically, I'd like to know what the << and >> imply. An example alias statement is,
alias x2_dac_data is << signal server.x2_dac_data : std_logic_vector(23 downto 0) >>; where server is an instantiated component and x2_dac_data is a signal with the component, but not listed in the port declaration.
I've reviewed Pedroni's text and a course guide, neither of which reference the << ... >> syntax as it relates to alias.
Thanks
2 Answers
The double Less-Thans and double Greater characters (<<, >>) enclose an External Name, which is a path name to a object (e.g. signal, constant, variable) through a design model's hierarchy. The intended use is for design verification, allowing a testbench to reach objects not visible at the top level of a design.
See Peter Ashenden and Jim Lewis The Designer's Guide to VHDL (3rd Ed.), Section 18.1 External Names and Doulos VHDL-2008: Easier to use, Hierarchical Names, or IEEE Std 1076-2008, 8.7 External names.
There's an example on Page 561 of The Designer's Guide to VHDL:
alias duv_data_bus is <<signal .tb.duv_rtl.data_bus : std_ulogic_vector(0 to 15)>>; The syntax is described on Page 560. Pages 559-562 are visible in the Google Book preview. The example found in The Designer's Guide to VHDL dealing with external names is also found in Chapter 2, Section 2.1 External Names of VHDL 2008 Just the New Stuff by the same authors and while without the EBNF syntax description goes further into the philosophy behind external names. Unfortunately the book's Google Book preview doesn't reach Section 2.1. Jim Lewis is organizing the P1076 Study Group of the IEEE VHDL Analysis and Standardization Group (VASG) responsible for developing the next revision of IEEE Std 1076-201X. Peter Ashenden is a long time contributor to the VHDL standardization effort as well.
A better solution than aliases to hierarchical signal references in packages: using a package to share signals between bfm-procedures and testbench toplevel. Example:
library ieee; use ieee.std_logic_1164.all; --VHDL 2008 with questasim package bfm is signal tb_ii_a : std_logic; signal tb_ii_b : std_logic; signal tb_oo_c : std_logic; procedure wiggle; end package; package body bfm is procedure wiggle; begin tb_oo_c <= force in '1'; wait for 10 ns; tb_oo_c <= force in '0'; wait for 10 ns; tb_oo_c <= force in tb_ii_a and tb_ii_b; end procedure; end package body; library ieee; use ieee.std_logic_1164.all; use std.textio.all; use std.env.all; library work; use work.bfm.all; entity tb; end tb; architecture tb_dut1 of tb is begin dut : entity work.dut port map( oo_a => tb_ii_a, -- output of dut input of tb bfm oo_b => tb_ii_b, -- output of dut input of tb bfm ii_c => tb_oo_c -- input of dut output of tb bfm ); testcase : process begin wiggle; wait for 100 ns; std.env.stop(0); end process; end architecture; 
