how to solve 4 bit full adder verilog

I am supposed to create 4 bit full adder verilog code in vivado.But when I try to test in the simulation.It give me z and x output.Which part of code I have to change to get an output in simulation

module my_full_adder( input A, input B, input CIN, output S, output COUT ); assign S = A^B^CIN; assign COUT = (A&B) | (CIN&(A^B)); endmodule 

This is the one bit full adder verilog code

I have check the schematic for this code and everything is correct.

module four_bit_adder( input [3:0] A, input [3:0] B, input C0, output [3:0] S, output C4 ); wire C1,C2,C3; my_full_adder fa0 (A[0],B[0],C0,S[0],C1); my_full_adder fa1 (A[1],B[1],C1,S[1],C2); my_full_adder fa2 (A[2],B[2],C2,S[2],C3); my_full_adder fa3 (A[3],B[3],C3,S[3],C4); endmodule 

Test bench

module test_4_bit( ); reg [3:0] A; reg [3:0] B; reg C0; wire [3:0] S; wire C4; four_bit_adder dut(A,B,C0,S,C4); initial begin A = 4'b0011;B=4'b0011;C0 = 1'b0; #10; A = 4'b1011;B=4'b0111;C0 = 1'b1; #10; A = 4'b1111;B=4'b1111;C0 = 1'b1; #10; end endmodule 

2 Answers

I don't have any idea about your testbench code but I think you have a mistake in your main code.Please try again with this code:

module fourbit_fulladder(Sum ,Cout , Cin , X ,Y); output [3:0]Sum; output Cout; input Cin; input [3:0]X,Y; wire C1,C2,C3; FullAdder_m FA1(Sum[0],C1,X[0],Y[0],Cin); FullAdder_m FA2(Sum[1],C2,X[1],Y[1],C1); FullAdder_m FA3(.S(Sum[2]),.Cout(C3),.A(X[2]),.B(Y[2]),.Cin(C2)); FullAdder_m FA4(.S(Sum[3]),.Cout(Cout),.A(X[3]),.B(Y[3]),.Cin(C3)); endmodule 

enter code here module fulladder( input [3:0] a, input [3:0] b, input cin, output [3:0] sum, output cout ); /*assign cin=0;*/ wire c1,c2,c3; adder fa0 (a[0],b[0],cin,sum[0],c1); adder fa1 (a[1],b[1],c1,sum[1],c2); adder fa2 (a[2],b[2],c2,sum[2],c3); adder fa3 (a[3],b[3],c3,sum[3],cout); endmodule first design full adder to implemet the above module adder( input [3:0] a, input [3:0] b, input cin, output [3:0] sum, output cout ); assign sum = a ^ b ^ cin; assign cout = (a&b) | (cin&(a^b)); endmodule ucf file NET "a[0]" LOC = "A10"; NET "a[1]" LOC = "D14"; NET "a[2]" LOC = "C14"; NET "a[3]" LOC = "P15"; NET "b[0]" LOC = "P12"; NET "b[1]" LOC = "R5"; NET "b[2]" LOC = "T5"; NET "b[3]" LOC = "E4"; NET "sum[0]" LOC = "U18"; NET "sum[1]" LOC = "M14"; NET "sum[2]" LOC = "N14"; NET "sum[3]" LOC = "L14"; NET "cout" LOC = "M13"; 

The above ucf file is for Spartan 6 board